Hirad Samavati received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1994 and the M.S. degree in electrical engineering from Stanford University, Stanford, CA, in 1996. He received his Ph.D. degree from Stanford in 2001 under supervision of Professor Thomas H. Lee at Stanford Microwave Integrated Circuits Laboratory.

He is currently at Atheros Communications, Sunnyvale, CA where he is designing radio frequency circuits for IEEE 802.11a/b/g compliant Wireless-LAN chipsets and beyond. During the summer of 1996, he was with Maxim Integrated Products, where he designed building blocks for a low-power infrared transceiver IC. His current research interests include RF circuits and analog and mixed-signal VLSI, particularly integrated transceivers for wireless communications. As part of his research at Stanford University, he built and tested a fully-integrated 5GHz CMOS wireless-LAN receiver.

Mr. Samavati received a departmental fellowship from Stanford University in 1995 and a fellowship from IBM Corp. in 1998. He is the winner of the ISSCC Jack Kilby outstanding student paper award for the paper "Fractal Capacitors" in 1998.

• T. Lee, H. Samavati, and H. Rategh "5-GHz CMOS wireless LANs," IEEE Transactions on Microwave Theory and Techniques, pp. 268-280, Jan. 2002.

• H. Samavati, H. Rategh, and T. Lee, "A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver,"International Solid-State Circuits Conference Digest, pp. 208-209, 2001. (Slides)

• H. Samavati, H. Rategh, and T. Lee, "A 5GHz CMOS Wireless-LAN Receiver Front-End," IEEE J. Solid-State Circuits, vol. 35, pp 765-772, May 2000.

• H. Rategh, H. Samavati and T. Lee, "A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5GHz Wireless LAN Receiver," IEEE J. Solid-State Circuits, vol. 35, pp 780-787, May 2000.

• H. Samavati, H. Rategh, and T. Lee, "A 12.4mW CMOS front-end for a 5GHz wireless-LAN receiver," Symp. VLSI Circuits Dig. Tech. Papers, pp. 87-90, June 1999. (Slides)

• H. Rategh, H. Samavati, and T. Lee, "A 5GHz, 32mW CMOS frequency synthesizer with an injection locked frequency divider," Symp. VLSI Circuits Dig. Tech. Papers, pp 113-116, June 1999. (Slides)

• H. Rategh, H. Samavati, and T. Lee, "A 5GHz, 1mW CMOS voltage controlled differential injection locked frequency divider," Proc. CICC, May 1999. (Slides)

• H. Samavati, A. Hajimiri, A. Shahani, G. Nasserbakht, and T. Lee, "Fractal capacitors," IEEE J. Solid-State Circuits, vol. 33, pp. 2035-2041, Dec. 1998.

• D. Shaeffer, A. Shahani, S. Mohan, H. Samavati, H. Rategh, M. Hershenson, M. Xu, C. Yue, D. Eddleman, and T. Lee, "A 115-mW, 0.5-mm CMOS GPS receiver with wide dynamic-range active filters," IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, Dec. 1998.

• A. Shahani, D. Shaeffer, S. Mohan, H. Samavati, H. Rategh, M. Hershenson, M. Xu, C. Yue, D. Eddleman, and T. Lee, "Low-power diverderless frequency synthesis using aperture phase detection," IEEE J. Solid-State Circuits, vol. 33, pp. 2232-2239, Dec. 1998.

• H. Samavati, A. Hajimiri, A. Shahani, G. Nasserbakht, and T. Lee, "Fractal capacitors," International Solid-State Circuits Conference, pp. 256-257, 1998. (Slides)

• D. Shaeffer, A. Shahani, S. Mohan, H. Samavati, H. Rategh, M. Hershenson, M. Xu, C. Yue, D. Eddleman,and T. Lee, "A 115mW CMOS GPS receiver," International Solid-State Circuits Conference Digest, pp. 122-123, 1998. (Slides)

  ---

  Thesis Abstract

  A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver

  (Slides)

  The growing popularity of notebook computers demands high data-rate wireless local area network (LAN) systems. The need for higher data-rate wireless products prompted the Federal Communications Commission (FCC) to release 300MHz of spectrum, now known as the unlicensed national information infrastructure (U-NII) band. Using this newly released frequency band, wireless LAN systems can provide data rates of several tens of megabits per second. The allocated frequencies partially overlap the European high performance radio LAN (HIPERLAN) frequency band. Designing a low-power receiver usable in these bands is quite a challenge. In this work, a fully-integrated 5GHz CMOS wireless-LAN receiver is introduced.

  The most commonly used receiver architecture is the superheterodyne architecture. However, in a monolithic superheterodyne implementation, image cancellation is difficult due to the design problems of on-chip filters. The use of image-reject architecture alleviates this problem to some extent. To augment the amount of image rejection beyond what is practically achieved by the image-reject architecture, a tracking notch filter is integrated with the low noise amplifier (LNA). The image-reject band of this filter is automatically tuned to the correct frequency using a low-power image-reject PLL. The filter also reduces the noise contribution of the cascode devices in the LNA core. The receiver is implemented in a 0.24-um CMOS technology and consumes 59mW of power and occupies 4mm^2 of die area. The overall image rejection is 53dB and the noise figure is 7.2dB. The system is highly linear and tolerates large blockers.

  In the receiver, self mixing of the local oscillator creates the well-known problem of DC offset. Various techniques for DC offset cancellation exist, but they all require large capacitors. On chip capacitors are crucial in analog circuit design in general, and RF design in particular. Capacitors can occupy considerable area, therefore an area-efficient linear capacitor is highly desirable. The problem is more pronounced in modern process technologies where the vertical spacing of the metal layers does not scale much, if at all. To address this problem, we propose linear capacitor structures using fractal geometries. These fractal capacitors exploit both lateral and vertical electric fields to increase the capacitance per unit area. Moreover, the capacitance density of fractal capacitors increases with technology scaling. Compared to standard parallel-plate capacitors, fractal capacitors have smaller parasitic bottom-plate capacitance.The capacitance density of the prototype fractal capacitor in this design is 3.5 times higher than a standard parallel-plate structure. We developed a CAD tool to automatically generate and analyze custom fractal layouts.